Added

• Add mtopei CSR
• Add mstatus and sstatus CSRs helpers for UBE, VS, UXL and SXL, and the corresponding tests
• Add pmpaddr16 ~ pmpaddr63 CSRs
• Add siselect CSR
• Add vsiselect CSR
• Add stopi CSR

Changed

• Fix the CSR masks to preserve all legal status bits
• Modify XS and SD bits to read-only summary fields instead of writable fields
• replaced paste crate with pastey to fix RUSTSEC-2024-0436

A new batch of RISC-V releases is now available at crates.io! Here we enumerate the most important changes, but please read the CHANGELOG.md files for further details.

riscv-types v0.1.0

This crate substitutes riscv-pac, which is now deprecated

riscv v0.16.0

• Added new CSRs (@0xllx0 @KushalMeghani1644)
• New rt and rt-v-trap features to opt-in riscv-rt-related code in riscv::pac_enum macro (@romancardenas)

riscv-rt v0.17.0

• New no-mhartid and no-xtvec features to support more targets (@Shatur)
• Fix v-trap core interrupt so RISCV_RT_BASE_ISA must be defined (@kurtjd)
• Fix stack allocation algorithm for multi-core targets without M extension (@romancardenas )

Added

• Add vstopi CSR
• Add dcsratch0 and dscratch1 CSRs
• Add new read-write_csr_as_usize macro for registers
• Add dpc CSR support for RISC-V
• Add Mtopi
• Added DCSR (Debug Control and Status Register) CSR support for the RISC-V
• Add miselect CSR
• Improved assembly macro handling in asm.rs
• New rt and rt-v-trap features to opt-in riscv-rt-related code in riscv::pac_enum macro.
• Add mvien + mvienh CSR

Changed

• Bump MSRV to 1.81 due to riscv-types
• Use riscv-types instead of riscv-pac
• Reexport only pac_enum macro from riscv-macros
• Fix broken links in register macro doc string.
• Moved macros from ./macros/ to ../riscv-macros/
• Updated the license to MIT or Apache-2.0
• Now, riscv::pac_enum macro only includes trap-related code if rt or rt-v-trap features are enabled.

A new batch of RISC-V releases is now available at crates.io! Here we enumerate the most important changes, but please read the CHANGELOG.md files for further details.

riscv v0.15.0

• @rmsyn added proxies to new CSRs.
• @romancardenas added new methods and associated functions that rely on riscv-pac abstractions for interrupts.
• @jsgf fixed a bug with the mcause bit mask.

riscv-peripheral v0.4.0

• @romancardenas added new constant methods to access registers for HART 0.

riscv-rt v0.16.0

This release features numerous exciting changes. The most important are:

• @bjoernQ added the final necessary changes to allow esp-riscv-rt to run on top of riscv-rt.
• @romancardenas added linker sections and adapted the boot process to resemble cortex-m-rt and esp-riscv-rt.
• @janderholm fixed a bug in the linker file. Also, the stack is now split into equal parts based on the number of hearts. In addition, the runtime now avoids some relative jumps to ease the linker placement of code.
• @jannic and @Dirbaio merged global_asm macro invocations to avoid potential undefined behavior in future Rust releases.

Other changes

• @Lumilesto fixed some links in the docs
• @gibbz00 improved the CI process with spelling checks and improved the docs of riscv-rt

Thank you to all the people who contributed to these releases!

Added

• New convenience try_new and new associated functions for Mtvec and Stvec.
• New methods and functions for enabling core interrupts in the mie and sie registers using the riscv_pac::CoreInterruptNumber trait.
• New riscv::interrupt::{is_interrupt_enabled, disable_interrupt, enable_interrupt} functions.
• New methods and functions for dealing with pending interrupts in mip and sip registers using the riscv_pac::CoreInterruptNumber trait.
• New riscv::interrupt::is_interrupt_pending function.
• New riscv::register::xip::clear_pending atomic function for mip and sip registers. This function is marked as unsafe, as its availability depends both on the target chip and the target interrupt source.
• Add mseccfg CSR
• Add mseccfgh CSR

Changed

• Use cfg(any(target_arch = "riscv32", target_arch = "riscv64")) instead of cfg(riscv).
• riscv::pac_enum(unsafe CoreInterrupt) now locates the vector table at the .trap.vector section instead of .trap.
• Allow all bits to be set in Mcause::from_bits on 64-bit targets.

Removed

• Removed custom build script, as cfg(riscv) is no longer necessary.
• All the fields of Mip and Sip CSR proxies are now read-only. This change is motivated to avoid clearing unwanted interrupts triggered between CSR reads and CSR writes.

A new batch of RISC-V releases are now available at crates.io! Here we enumerate the most important changes, but please read the CHANGELOG.md files for further details

riscv v0.14.0

@rmsyn added new CSRs. Also, MSRV is now 1.67

riscv-peripheral v0.3.0

This crate experienced a full rework, so the code corresponding to RISC-V peripherals is more natural for PACS generated with svd2rust

riscv-rt v0.15.0

We added the device and memory features to allow PACs to simplify the linking process, similar to cortex-m-rt. If you enable these features, the link.x file will include the device.x and/or memory.x files. In this way, just including link.x in your binary is enough.

The __pre_init symbol has disappeared from riscv-rt by default. If you need it, you must activate the pre_init feature. Also, note that the riscv_rt::pre_init has been deprecated, as it is unsound to execute Rust code before RAM initialization. Instead, use assembly.

We removed weak symbols, as currently stable Rust does not support weak linkage and LTOs. Now, we use _default_* symbols. Once weak linkage is available in stable Rust, we plan to go back to weak symbols. Thanks, @rslawson !

Added

• CSR helper macro write_composite_csr for writing 64-bit CSRs on 32-bit targets.
• Write utilities for mcycle, minstret
• Add senvcfg CSR
• Add scontext CSR
• Add mconfigptr CSR
• Bump MSRV to 1.67.0 for log to ilog name change
• Add mtval2 CSR

Changed

• Simplify riscv::interrupt::machine::nested

riscv 0.12.0

• CSR writes are now all unsafe. Users can open an RFC to nominate certain CSRs to be safe (#209)
• All CSR fields are now generated using macros (thanks, @rmsyn !)
• PACs can now use the RISCV_MTVEC_ALIGN environment variable to set the vector table byte alignment ((thanks, @ia0 !)

riscv-rt 0.13.0

• Compatibility with RV32E and RV64E!
• Linker script is now more aligned with cortex-m-rt

riscv-target-parser 0.1.0

New utility crate to assist in build scripts of the RISC-V ecosystem. It is useful for determining which extensions are available, the base ISA of the target, etc.

riscv-peripheral 0.2.1 and riscv-semihosting 0.1.3

Update dependencies

Added

• CSR helper macro to check for platform implementation

Changed

• Make all CSR writes unsafe by default (#209)
• Use RISCV_MTVEC_ALIGN to control the alignment constraint of the vector table
• Simplify register macros with cfg field
• Align assembly functions with cortex-m
• Use CSR helper macros to define marchid register
• Re-use try_* functions in mcountinhibit
• Use CSR helper macros to define mcause register
• Use CSR helper macros to define medeleg register
• Use CSR helper macros to define mideleg register
• Use CSR helper macros to define mcounteren register
• Use CSR helper macros to define mie register
• Use CSR helper macros to define mimpid register
• Use CSR helper macros to define misa register
• Use CSR helper macros to define mip register
• Use CSR helper macros to define mstatus register
• Use CSR helper macros to define mstatush register
• Use CSR helper macros to define mtvec register
• Use CSR helper macros to define mtvendorid register
• Use CSR helper macros to define satp register
• Use CSR helper macros to define pmpcfgx field types
• Use CSR helper macros to define scause field types
• Use CSR helper macros to define sie register
• Use CSR helper macros to define scounteren field types
• Use CSR helper macros to define sip register
• Use CSR helper macros to define sstatus field types
• Use CSR helper macros to define stvec field types
• Add remaining pmpcfg CSRs from RISC-V privileged spec

Changed

• Update critical-section to 1.2.0

New features

riscv 0.12.0

• Support for target-dependent external interrupt and exception numbers
• riscv-macros for helping during the definition of custom interrupt and exception sources
• Macros for automating the definition of new CSRs

riscv-pac 0.2.0

• Enumeration of common errors for RISC-V targets at the register level
• All PAC traits now work with usize numbers
• New ExceptionNumber trait for custom exception numbers

riscv-peripheral 0.2.0

• Adapt to new changes in the RISC-V ecosystem

riscv-rt 0.13.0

• Now exceptions rely on the _dispatch_exception function
• Now interrupts rely on the _dispatch_interrupt function
• While the crate provides a default implementation for the previously mentioned functions, you can skip these functions with the new no-exceptions and no-interrupts features. This way, you can adapt riscv-rt to target-specific sources.
• New pre_init_trap to detect early errors during the boot process.
• Vectored interrupts handling is now available under the v-trap feature!
• New core_interrupt, external_interrupt, and exception macros for defining interrupt and exception handlers
• New u-boot feature to execute U-boot binaries.

Added

• riscv-macros crate for riscv-pac enums.
• Bump MSRV to 1.61.
• Implementation of riscv-pac traits for Interrupt and Exception enums.
• Tests for the riscv-pac trait implementations of Interrupt and Exception enums.
• Add Mcause::from(usize) for use in unit tests
• Add Mstatus::from(usize) for use in unit tests
• Add Mstatus.bits()
• Add Eq and PartialEq for pmpcfgx::{Range, Permission}
• Add Mstatus::update_* helpers to manipulate Mstatus values without touching the CSR
• Export riscv::register::macros module macros for external use
• Add riscv::register::mcountinhibit module for mcountinhibit CSR
• Add Mcounteren in-memory update functions
• Add Mstatus vector extension support
• Add fallible counterparts to all functions that panic
• Add riscv-pac as a dependency
• Add CSR-defining macros to create in-memory types

Fixed

• Fixed sip::set_ssoft and sip::clear_ssoft using wrong address
• Fixed assignment in mstatus unit tests.
• delay implementation does not use binary labels in inline assembly.

Changed

• Made asm::wfi, fence, fence_i and sfence safe (ie, removed unsafe from their definitions)
• Made cfg variable selection more robust for custom targets

Added

• Add asm::ecall(), a wrapper for implementing an ecall instruction
• Add nested function for nested ISRs in interrupt::machine and interrupt::supervisor
• s-mode feature for reexporting interrupt::machine or interrupt::supervisor to interrupt
• Support for supervisor-level interrupts in interrupt::supervisor
• Add CI workflow to check that CHANGELOG.md file has been modified in PRs
• Add read_csr_as_rv32, set_rv32, and clear_rv32 macros
• Add mstatus::uxl and mstatus::sxl
• Add mstatus::ube, mstatus::sbe, and mstatus::mbe endianness bit fields
• Add mstatush registers (RISCV-32 only)
• Add asm::fence(), a wrapper for implementing a fence instruction
• Add asm::fence_i(), a wrapper for implementing a fence.i instruction
• Add TryFrom implementation for mcause::{Interrupt, Exception} and scause::{Interrupt, Exception}

Changed

• Cargo workspace for riscv and riscv-rt
• Update embedded-hal dependency to v1.0.0 (bumps MSRV to 1.60)
• misa::MXL renamed to misa::XLEN
• Removed bit_field dependency
• CI actions updated. They now use checkout@v3 and dtolnay/rust-toolchain.
• mcause::{Interrupt, Exception} and scause::{Interrupt, Exception} now implement From trait for usize
• Set safety of asm::nop and asm::delay functions to safe.

Fixed

• Fix scause::Exception missing LoadMisaligned
• Fix scause::Exception missing SupervisorEnvCall
• Removed user-level interrupts from mcause::Interrupt and scause::Interrupt
• Removed user-level interrupts from mstatus
• Removed machine environment call delegation from medeleg
• Removed user-level interrupts from machine and supervisor mode interrupt-related registers.

Removed

• User mode registers removed, as they are no longer supported in RISC-V
• FCSR register operations removed to avoid UB (#148)

release v0.10.1 with critical section bug

Fixed

• Fix implementation for SingleHartCriticalSection

120: release v0.10.0 r=almindor a=almindor

Fixed #119

Co-authored-by: Ales Katona [email protected]

Added

• critical-section-single-hart feature which provides an implementation for the critical_section crate for single-hart systems, based on disabling all interrupts.

Fixed

• Fix asm::delay() to ensure count register is always reloaded
• Fix reading marchid and mimpid (#107)

Removed

• set_msoft, clear_msoft, set_mtimer and clear_mtimer removed as part of fixing issue #62

112: Propose to release a version riscv v0.8.1 r=almindor a=luojia65

The riscv crate includes an important fix (#107) where the RustSBI community would leverage the use of. However, the latest release v0.8.0 did not include this fix. In this pull request we want to propose to release a new version of riscv crate to include at least this fix, so that RustSBI community would write correct implemenations based on this crate.

Notes to CHANGELOG.md: the release date 2022-10-06 can always be changed.

r? @Disasm

Co-authored-by: luojia65 [email protected]

102: Prepare v0.8.0 release r=almindor a=Disasm

Co-authored-by: Vadim Kaushan [email protected]

Added

• Add #[cfg(riscv32)] to pmpcfg1 and pmpcfg3 modules
• Add enums Range, Permission for PMP configuration
• Add set_pmp() and clear_pmp() functions to pmpcfg(x) modules
• Add struct Pmpcsr and is returned from pmpcfgx::read()
• Add singleton! macro
• Add delay structure and methods using embedded-hal traits and mcycle register
• Add asm::delay() function for assembly-based busy-loops
• Add asm::nop(), a wrapper for implementing a nop instruction
• Add missing #[inline] attribute to register reads, type conversations and interrupt::free

Changed

• Use new asm! instead of llvm_asm!
• Change pmpcfgx::read() macro to read_csr_as!() from read_csr_as_usize!()
• Inline assembly is now always used
• Update Minimum Supported Rust Version to 1.59

Fixed

• Fix sfence.vma operand order

Removed

• Remove inline-asm feature which is now always enabled

Added

• Add medeleg register
• Add cycle[h], instret[h] and mcounteren
• Add additional binaries for floating-point ABIs
• Add support for mxr
• Add support for mprv

Changed

• Fix scause::set
• Various formatting and comment fixes
• Update bare-metal to v1.0.0 removing Nr trait
• Build targets on docs.rs are now RISC-V targets other than default ones

Changed

• Mtvec::trap_mode(), Stvec::trap_mode() and Utvec::trap_mode() functions now return Option<TrapMode> (breaking change)
• Updated Minimum Supported Rust Version to 1.42.0
• Use llvm_asm! instead of asm!

Removed

• vexriscv-specific registers were moved to the vexriscv crate

Added

• Added vexriscv-specific registers

Added

• Added riscv32i-unknown-none-elf target support
• Added user trap setup and handling registers
• Added write methods for the mip and satp registers
• Added mideleg register
• Added Changelog

Changed

• Fixed MSRV by restricting the upper bound of bare-metal version