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iced is a blazing fast and correct x86 (16/32/64-bit) instruction decoder, disassembler and assembler written in C#. - 👍 Supports all Intel and AMD instructions - 👍 Correct: All instructions are tested and iced has been tested against other disassemblers/assemblers (xed, gas, objdump, masm, dumpbin, nasm, ndisasm) and fuzzed - 👍 100% C# code - 👍 The formatter supports masm, nasm, gas (AT&T), Intel (XED) and there are many options to customize the output - 👍 The decoder decodes >130 MB/s - 👍 Small decoded instructions, only 40 bytes and the decoder doesn't allocate any memory - 👍 Create instructions with code assembler, eg. `asm.mov(eax, edx)` - 👍 The encoder can be used to re-encode decoded instructions at any address - 👍 API to get instruction info, eg. read/written registers, memory and rflags bits; CPUID feature flag, control flow info, etc - 👍 Supports `.NET Standard 2.0/2.1+` and `.NET Framework 4.5+` - 👍 License: MIT
Last release 3 years ago
no release in 18 months
Release timing varies
gaps range from 2 weeks to 10 months
Some releases are documented
notes for 10 of 29 stable releases
Nothing withdrawn
no release was ever pulled
8 years old
29 releases · first in 2018
Fixed BlockEncoder returning an error when trying to encode a 32-bit branch from 0 -> FFFFFF00 #511
Added new Intel instructions #428
AVX-VNNI-INT16SHA512SM3SM4TSEOne column per quarter.
Added new Intel instructions #400
AMX-COMPLEXCMPccXADD instructions #374hashbrown dependency that was used if no_std + serde has now been removed.Added new AMD instructions #369
RMPQUERYAMX-FP16AVX-IFMAAVX-NE-CONVERTAVX-VNNI-INT8CMPCCXADDMSRLISTPREFETCHITIRAO-INTWRMSRNSImproved BlockEncoder speed #262 , #265
BlockEncoder speed #262, #265
Decoder speed (100MB/s -> 130MB/s, .NET 6 x64) #266, #267
XSHA512 alias #261a.zero_bytes()) that can be used as an assembler label #272CodeAssembler::assemble_options() and an API to get the address of labels after the code has been assembled #273Removed deprecated Instruction::with_* methods (use with{1,2,3,4,5}() instead)
PADLOCK instructions, added missing XSHA512 instruction #260 (VIA info from @tremalrik)IsJcxShort/IsLoopcc/IsLoop methods/props #227 (Credit @am0nsec), #259CodeAssembler traits public #236 (Credit @Kixiron)Instruction/Register fns const #240 (Credit @i509VCB)HashMap (hashbrown crate if no_std) dependency from block_encoder feature #248
no_std on Windows)Instruction::with_* methods (use with{1,2,3,4,5}() instead)BigInt is supported by default now #258Added Intel Knights Corner (KNC) instructions
DecoderOptions::KNC to the Decoder constructormvex feature must also be enabled to decode KNC instructionsmypy reporting errors, see hereserde feature): json deserialization (Instruction) is faster (json is still inefficient and slow, though)Jcc, SETcc, CMOVcc, REP{,N}E aliases (eg. a.jz(lbl))a.vex()/a.evex() fns to select VEX or EVEX encodingRust: Added Instruction::with{1,2,3,4,5}() methods to create instructions. The older methods with longer names have been deprecated.
let mut a = CodeAssembler::new(64)?;
a.xor(ecx, ecx)?;
a.add(byte_ptr(rdx + r15 * 8 + 7), 0x10)?;
assert_eq!(a.instructions().len(), 2);
let bytes = a.assemble(0x1234_5678)?;
assert_eq!(bytes, b"\x31\xC9\x42\x80\x44\xFA\x07\x10");code_asm feature which is disabled by default.Instruction::with{1,2,3,4,5}() methods to create instructions. The older methods with longer names have been deprecated.
// old:
let _ = Instruction::try_with_reg_reg_u32(Code::Imul_r16_rm16_imm16, Register::CX, Register::DX, 0x5AA5)?;
// new: (the '3' suffix means '3 operands')
let _ = Instruction::with3(Code::Imul_r16_rm16_imm16, Register::CX, Register::DX, 0x5AA5)?;
// A number suffix (`u32`, `u64`, `i64`) is sometimes needed to help the compiler:
let _ = Instruction::with2(Code::Mov_r64_imm64, Register::RAX, 0x1234_5678_9ABC_DEF0u64)?;Instruction can be serialized/deserialized with pickle (Credit: @paulfariello)Instruction::is_string_instruction() (Credit: @woodruffw) which returns true if it's eg. SCASB, MOVSQ, or any other string instruction.serde feature added to serialize/deserialize InstructionAdded Intel AVX512-FP16 instructions
AVX512-FP16 instructions0F 0E and 0F 0F instructions (enable with DecoderOptions.Udbg/::UDBG), see https://github.com/chip-red-pill/udbgInstrMemoryOperand.ctor_u64() to create an instance with an unsigned displRust: Decoder perf improvements
Decoder perf improvements
VPCMP{U,}{B,W,D,Q} pseudo ops, eg. VPCMPLEBgas formatter updated to add SYSEXIT L/Q suffixes in 64-bit mode instead of a REX.W prefixNothing published for this version
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