NewYour coding agent can read the release notes before it upgrades.Set up the MCP server →
pub.dev · #2841 most downloaded on pub.dev
The Rapid Open Hardware Development (ROHD) framework, a framework for describing and verifying hardware.
Last release 19 days ago
18 Sep 2026
Release timing varies
gaps range from 9 days to 9 months
Nearly every release is documented
notes for 26 of 26 stable releases
Nothing withdrawn
no release was ever pulled
5 years old
26 releases · first in 2021
One column per quarter.
Throw an exception for duplicate interface port names by @aishasalim in #694
assignSubset inputs and preserve isolated bit drivers by @mkorbel1 in #711Full Changelog: v0.6.10...v0.6.11
NetlistSynthesizer for generating JSON netlists, with configurable synthesis passes, validation, and hierarchy support (https://github.com/intel/rohd/pull/675).DuplicatePortNameException for duplicate Interface port names in all build modes, replacing an assertion that was disabled in release mode (https://github.com/intel/rohd/pull/694).rohd_waveform package (https://github.com/intel/rohd/pull/681).rohd_hierarchy, rohd_waveform, and rohd_devtools_widgets, each at 0.1.0. See the release guide for package-specific release and tagging conventions.reserved and renameable signals with matching generated base names to share a declaration, including internal signals and port aliases, in generated outputs. Separate aliases may disappear and connected same-name reserved signals no longer cause naming errors; unrelated reserved-name collisions still fail (https://github.com/intel/rohd/pull/712).buildOnly mode, required in native CI and explicitly skipped locally when Verilator is unavailable (https://github.com/intel/rohd/pull/714).Logic.assignSubset connections into submodule inputs (https://github.com/intel/rohd/pull/711).Add coverage status badge to readme ( #270 ) by @maifeeulasad in #658
Consts by @mkorbel1 in #679Full Changelog: v0.6.9...v0.6.10
Logic.replicate(1) and same-width signExtend to return the original signal, eliminating redundant replication modules and generated SystemVerilog (https://github.com/intel/rohd/pull/689).Consts, zero shifts, and muxes with constant controls (https://github.com/intel/rohd/issues/429).Const values cannot be changed through put or inject, including through another Logic driven by a Const (https://github.com/intel/rohd/issues/486).Const preferred radix control for generated literals, normalized Const names to reflect their displayed radix, and enhanced LogicValue.toRadixString to omit its width and radix decorator or digit separators (https://github.com/intel/rohd/issues/601).input logic, output logic, and inout wire declarations (https://github.com/intel/rohd/pull/678, https://github.com/intel/rohd/pull/687).rohd_hierarchy package for compact hierarchy dictionaries, canonical occurrence addresses, hierarchy search, and netlist adapters (https://github.com/intel/rohd/pull/653).Logic.getRange and slice on filled Consts to return direct constants instead of constructing BusSubset modules (https://github.com/intel/rohd/pull/677).LogicArrays and net buses (e.g. from bit-blasting, aggregate connections, assignSubset) into inline concatenations on their consuming connections, eliminating unnecessary intermediate declarations, assigns, and net_connects when it is safe to do so (https://github.com/intel/rohd/pull/663).Add automation for code coverage in pushes by @maifeeulasad in #646
Full Changelog: v0.6.8...v0.6.9
LogicStructure elements (https://github.com/intel/rohd/pull/650).Fix typos by @antonkesy in #642
Full Changelog: v0.6.7...v0.6.8
Deprecate PairInterface.modify in favor of uniquify on addSubInterface by @mkorbel1 in #620
PairInterface.modify in favor of uniquify on addSubInterface by @mkorbel1 in #620Conditional.driveX by @mkorbel1 in #623WriteAfterReadException message with trace of involved assignments by @mkorbel1 in #624PairInterfaces by @mkorbel1 in #628packed on LogicStructures on output ports reused inside and out cause build trace failures by @mkorbel1 in #631Full Changelog: v0.6.6...v0.6.7
LogicStructures that contain elements which are ports could cause incorrect name selection in generated outputs (https://github.com/intel/rohd/pull/630).packed on output port LogicStructures being accessed both inside and outside of its parent module could cause build trace failures (https://github.com/intel/rohd/pull/631).LogicStructure ports could generate illegal SystemVerilog with slicing (https://github.com/intel/rohd/pull/629).LogicValue.ofRadixString could return incorrect values for invalid inputs instead of throwing an exception (https://github.com/intel/rohd/issues/616).PairInterfaces so that driveOther, receiveOther, etc. properly apply recursively to sub-interfaces as well (https://github.com/intel/rohd/pull/628). Note that any code that relied on or expected this missing capability may need to be updated.PairInterface.modify in favor of using uniquify on PairInterface.addSubInterface (https://github.com/intel/rohd/pull/620).Conditionals (https://github.com/intel/rohd/pull/623).hierarchicalName API to Module to make it easier to get the full hierarchical name of a module instance (https://github.com/intel/rohd/pull/635).WriteAfterReadExceptions to include a trace of conditional assignments involved in the execution (https://github.com/intel/rohd/pull/624).Fixing selecting the module and reflecting the respective signal table by @aneriach in #612
cloneing for Interfaces and Logics and APIs that leverage the new capabilities (https://github.com/intel/rohd/pull/614).
Interfaces and Logics (and derivative classes) to implement a clone function, to enable better APIs and reuse in various scenarios.PairInterface.clone constructor in favor of new clone method on PairInterface instances.addTyped* functions on Module which will create a clone of original source for ports. This also supports LogicStructures as ports.addInterfacePorts and addPairInterfacePorts functions on Module which wrap connectIO and pairConnectIO, respectively, to make adding interfaces on Modules easier and more consistent with creation of other ports.reserved names) that were part of LogicStructures to include the name of the parent structure as a prefix.packed to base Logic, which just returns itself, so that it can safely be called on any Logic without first checking the type.bug fix for zero value toRadixString() by @desmonddak in #606
Full Changelog: v0.6.4...v0.6.5
LogicValues could result in toRadixString() returning output an empty String instead of "0" (https://github.com/intel/rohd/pull/606).Deprecate Port and move to Logic.port for API consistency by @lucasphillips in #575
LogicStructure.previousValue by @mkorbel1 in #565Port and move to Logic.port for API consistency by @lucasphillips in #575Pipeline by @mkorbel1 in #588FiniteStateMachine upgrades by @mkorbel1 in #593Full Changelog: v0.6.3...v0.6.4
setupActions to FiniteStateMachine so that "common" or "default" actions can be grouped in one place instead of repeated in each State (https://github.com/intel/rohd/pull/593).LogicStructure.previousValue would actually return the current value instead of the previous one (https://github.com/intel/rohd/pull/565).Pipeline where cross-stage references could be incorrectly resolved (https://github.com/intel/rohd/pull/588).SynthBuilder.multi to generate outputs (e.g. SystemVerilog) for multiple top-level modules simultaneously, with shared uniquification across them. Deprecated getFileContents in favor of getSynthFileContents which provides SynthFileContents objects with more context than just the String contents. Also, improved modularity and organization of the "synth" infrastructure to make extension to additional generated outputs easier (https://github.com/intel/rohd/pull/598).Combinationals are used (https://github.com/intel/rohd/pull/602).LogicValue.toRadixString with more options to make usage easier and more flexible (https://github.com/intel/rohd/pull/583).Port in favor of Logic.port, making the APIs more consistent (https://github.com/intel/rohd/pull/575).Bug fix for withSet in LogicStructure. by @kimmeljo in #561
Full Changelog: v0.6.2...v0.6.3
withSet on LogicStructures could sometimes attempt to access the wrong range, causing unexpected exceptions (https://github.com/intel/rohd/pull/561).flop and FlipFlop would generate SystemVerilog with an asynchronous reset even if asyncReset was set to false (https://github.com/intel/rohd/pull/564).Transition to using a different addition syntax for lint avoidance by @mkorbel1 in #478
VcdParser by @mkorbel1 in #557Full Changelog: v0.6.1...v0.6.2
Simulator.reset (https://github.com/intel/rohd/issues/556).Fix bug in SSA discovery when LogicStructure s are used by @mkorbel1 in #540
LogicStructures are used by @mkorbel1 in #540Module.build didn't follow through structs containing ports properly, plus improved debug messaging. by @mkorbel1 in #541Logic.named and broaden clone by @mkorbel1 in #550Full Changelog: v0.6.0...v0.6.1
Logic.named and broadened API for clone to make duplicating and naming signals more convenient and succinct (https://github.com/intel/rohd/pull/550).LogicValue.toRadixString to gracefully handle invalid values (x and z) for radix-10 strings, rather than throwing an exception (https://github.com/intel/rohd/pull/543).Module.build fails due to a PortRulesViolationException (https://github.com/intel/rohd/pull/541).Module.build could sometimes fail to properly trace hierarchy through LogicStructures, cause false build failures (https://github.com/intel/rohd/pull/541).Combinational.ssa could sometimes fail to properly identify driver logic when LogicStructures were used (https://github.com/intel/rohd/pull/540).Deprecated CustomSystemVerilog in favor of SystemVerilog, which has similar functionality but supports inOut ports, and collapses all ports into a sin…
LogicNet, inOuts, and TriStateBuffer to enable multi-directional wires, ports, and drivers. Includes support for "wire-only" operations supporting multiple drivers.CustomSystemVerilog in favor of SystemVerilog, which has similar functionality but supports inOut ports, and collapses all ports into a single ports argument, as well as some other new features like custom definitions and parameter passthroughs.ExternalSystemVerilogModule and InlineSystemVerilog now extend SystemVerilog instead of CustomSystemVerilog, meaning the instantiationVerilog API arguments have been modified.Interface.connectIO has an additional optional named argument for inOutTags. Implementations of Interface which override connectIO will need to be updated.expressionlessInputs may not have been honored in non-inline custom SystemVerilog modules.xor between two LogicValues could cause an exception due to a false width mismatch.Synthesizer.synthesize and down the stack to use a Function to calculate the instance type of a module instead of a Map look-up table.srcConnections API to Logic to make it easier to trace drivers of subtypes of Logic which contain multiple drivers.Const constructor updated so that specified width takes precedence over the inherent width of a provided LogicValue val.asyncReset option in places where sequential reset automation was already present.Sequential has new added strictness checking when triggers and non-triggers change simultaneously (in the same Simulator tick) when it may be unpredictable how the hardware would synthesize or sample the inputs. In these scenarios, Sequential will interpret affected inputs as X, thus driving Xs on affected outputs instead of just picking an order. Descriptions that properly imply asynchronous resets are predictable and therefore unaffected.Simulator now occur in the mainTick phase. This API will generally continue to work as expected and as it always has, but in some scenarios could slightly change the behavior of existing testbenches.Simulator.injectEndOfTickAction which behaves similarly to Simulator.injectAction, except it registers the event to occur at the end of the tick rather than in the main phase. This is useful for some specific simulation situations like cosimulation, but not generally expected to be used for "normal" testbench development.Simulator.run now yields execution of the Dart event loop prior to beginning the simulation. This makes actions taken before starting the simulation more predictable, but may slightly change behavior in existing testbenches that relied on a potential delay.WaveDumper.Sequential.multi for cases where synthesis may interpret an inverted posedge as different from a negedge.resetValues would not take effect in Pipelines.Sequential may not generate X's if one trigger is valid and another trigger is invalid.getRange on LogicStructures and LogicArrays could access the wrong set of signals (https://github.com/intel/rohd/pull/499).assignSubset API to Logic and LogicStructure which behave similarly to the already-present API in LogicArray (https://github.com/intel/rohd/pull/502).Module for inputs and inOuts (https://github.com/intel/rohd/pull/503).LogicValue to enable conversion to and from various different radix strings.Simulator to halt (https://github.com/intel/rohd/pull/515).Added beta version of the ROHD DevTools Extension to aid in ROHD hardware debug by displaying module hierarchy and signal information visually and int
abs()) to both Logic and LogicValue (https://github.com/intel/rohd/pull/442).assignSubset for performing an assignment on a subset of a LogicArray (https://github.com/intel/rohd/pull/456).Logics and LogicArrays (https://github.com/intel/rohd/pull/473).Added APIs for accessing indices of a List using another Logic: Logic.selectFrom and List .selectIndex ( ).
List<Logic> using another Logic: Logic.selectFrom and List<Logic>.selectIndex (https://github.com/intel/rohd/pull/438).isZero to LogicValue.Pipeline abstraction via bug fixes, better error checking, improved documentation, and new APIs (https://github.com/intel/rohd/pull/447).Combinational.ssa (https://github.com/intel/rohd/pull/443).Simulator.endSimulation API to return a Future which completes once the simulation has ended (https://github.com/intel/rohd/pull/455).LogicStructures (e.g. for verification) could add additional hardware (which did not affect functionality) and also cause unexpected behavior on previousValue (https://github.com/intel/rohd/issues/457).Logic (e.g. changed, previousValue) could have incorrect behavior after a Simulator.reset (https://github.com/intel/rohd/pull/458).LogicValue.clog2 was inaccurate in rare scenarios.LogicValues.BigInts and LogicValues could result in incorrect arithmetic operations.FiniteStateMachine-generated mermaid diagrams were missing "default next state" cases (https://github.com/intel/rohd/pull/454).z (floating) if explicitly connected to a constant z (https://github.com/intel/rohd/pull/441).Fixed bugs and improved controllability around naming of internal signals and collapsing of inlineable functionality, leading to significantly more re
+ and << (https://github.com/intel/rohd/pull/423).Deprecated getReceivers, getDrivers, and getConditionals in always blocks like Combinational and Sequential in favor of simpler and more efficient API…
LogicArray for N-dimensional packed and unpacked (and mixed) arrays. Added LogicStructure for grouping sets of related signals together in a convenient way (https://github.com/intel/rohd/pull/375).ConditionalGroup which can group a collection of other Conditionals into one Conditional object.ConditionalAssign now return a Conditional, such as the < operator for Logic.LogicValue.of which now accepts a dynamic input and tries its best to build what you're looking for. Added LogicValue.ofIterable to replace the old LogicValue.of.previousValue to Logic to make testbench and modelling easier for things like clock edge sampling.Combinational sensitivities are implemented to improve performance and prevent some types of simulation/synthesis mismatch bugs. Added Combinational.ssa as a method to safely build procedural logic. Combinational will now throw fatal exceptions in cases of "write after read" violations. (https://github.com/intel/rohd/pull/344)getReceivers, getDrivers, and getConditionals in always blocks like Combinational and Sequential in favor of simpler and more efficient APIs receivers, drivers, and conditionals.incr, decr, mulAssign, and divAssign have been modified.IfBlock with If.block (deprecated IfBlock).StateMachine with FiniteStateMachine (deprecated StateMachine).FiniteStateMachine and Pipeline. Deprecated clk on FiniteStateMachine and Pipeline.FiniteStateMachine.PairInterface to make it easier to build and use simple Interfaces.connectIO in Interface now accepts Iterables instead of only Sets.Exceptions throughout to provide more specific information about errors and make them easier to catch and handle.getRange, swizzle, slice, etc.).LogicValues from a Random.LogicValue and Logic.equalsWithDontCare to LogicValue for comparisons where invalid bits are "don't-care".flop function to construct FlipFlops in an easier way.cases function to construct simple Case statements in an easier way.Sequential and flip flops.tryInput and tryOutput to Module and tryPort to Interface to more easily handle conditionally present ports by leveraging Dart's null safety by returning null if the port does not exist (instead of an exception).gt and gte to Logic to make APIs more consistent.clog2 to LogicValue.neq and pow to both Logic and LogicValue.LogicValue implement Comparable, enabling things like sorting.WaveDumper to recursively create necessary directories for specified output paths.SynthBuilder would not flag an error when run on a Module that hadn't yet been built (https://github.com/intel/rohd/issues/246).- sign in output SystemVerilog.Ifs that are illegally constructed throw an Exception (https://github.com/intel/rohd/issues/382).FiniteStateMachine could create an inferred latch (https://github.com/intel/rohd/pull/390).Case statements with multiple matches would throw an Exception instead of driving x on the output, which could cause spurious crashes during glitch simulation (https://github.com/intel/rohd/issues/107).Case and CaseZ would not use the properly edge-sampled value in Sequential blocks (https://github.com/intel/rohd/issues/348).z instead of x on outputs (https://github.com/intel/rohd/issues/235).Deprecated Logic.hasValidValue and Logic.isFloating in favor of similar operations on Logic.value ( ).
Conditional operations similar to ++x (incr), --x (decr), x *= (mulAssign), and x /= (divAssign) to Logic (https://github.com/intel/rohd/issues/141).Conditional more succinctly via Else.s (https://github.com/intel/rohd/issues/225).Combinationals were excessively pessimistic (https://github.com/intel/rohd/issues/233).Logic.put to include context on which signal was affected to help with debug (https://github.com/intel/rohd/pull/243).WaveDumper to only periodically write data to the VCD file to improve performance (https://github.com/intel/rohd/pull/242).endIndex in getRange an optional positional argument with a default value of width, enabling a more convenient method for collecting all bits from some index until the end (https://github.com/intel/rohd/issues/228).Simulator so that it would await asynchronous registered actions (https://github.com/intel/rohd/pull/252).Logic.hasValidValue and Logic.isFloating in favor of similar operations on Logic.value (https://github.com/intel/rohd/issues/198).Logic.isIn, which generates logic computing whether the signal is equal to any values in a (optionally mixed) list of constants or other signals (https://github.com/intel/rohd/issues/7).Fixed a bug where Modules could have invalid names in generated SystemVerilog ( ).
Modules could have invalid names in generated SystemVerilog (https://github.com/intel/rohd/issues/138).Logics could have invalid names in generated SystemVerilog.Logic via another Logic (https://github.com/intel/rohd/issues/153).Exceptions in ROHD with better error messages and more granular exception types to make handling easier.Logic via a constant values (https://github.com/intel/rohd/pull/208).Logic by a constant would throw an exception (https://github.com/intel/rohd/issues/170).Logics so that connected Logics share an underlying value-holding entity (https://github.com/intel/rohd/pull/199). One significant implication is that modifying a value of a Logic (e.g. via put or inject) will now affect the value of both downstream and upstream connected Logics instead of only downstream. This change also can significantly improve simulation performance in connection-heavy designs. Additionally, this change helps mitigate an issue where very long combinational chains of logic can hit the stack size limit (https://github.com/intel/rohd/issues/194).LogicValues would convert to incorrect int values (https://github.com/intel/rohd/issues/212).BigInt to perform unsigned conversion to an int.Conditional types (e.g. If) which have only a single Conditional more succinctly (https://github.com/intel/rohd/issues/12).LogicValue for performance (https://github.com/intel/rohd/pull/215).LogicValue called LogicValue.empty (https://github.com/intel/rohd/issues/202).LogicValues could have unequal hash codes (https://github.com/intel/rohd/issues/206). The fix also improved internal representation consistency for LogicValues, which could provide a significant performance improvement when wide values are used often.Deprecation: Improved naming of ports on basic gates, old port names remain accessible but deprecated for now ( ).
Combinational could have an incomplete sensitivity list causing incorrect simulation behavior (https://github.com/intel/rohd/issues/158).Combinational (https://github.com/intel/rohd/issues/106).Logic or LogicValue (https://github.com/intel/rohd/issues/99).SynthesisResults from the SynthBuilder, making it easier to generate SystemVerilog modules into independent files (https://github.com/intel/rohd/issues/172).topModuleName to definitionName in ExternalSystemVerilogModule (https://github.com/intel/rohd/issues/169).mux function as a shortcut for building a Mux and returning the output of it (https://github.com/intel/rohd/issues/13).Added the StateMachine abstraction for finite state machines.
StateMachine abstraction for finite state machines.% operator.WaveDumper to write to the .vcd file asynchronously to improve simulation performance while waveform dumping is enabled (https://github.com/intel/rohd/issues/3)Fixed a bug (introduced in v0.3.0) where WaveDumper doesn't properly dump multi-bit values to VCD ( ).
WaveDumper doesn't properly dump multi-bit values to VCD (https://github.com/intel/rohd/issues/129).Deprecation: Aligned LogicValue to Logic by renaming length to width.
LogicValue and LogicValues into one type called LogicValue.LogicValue to Logic by renaming length to width.Logic.put no longer accepts List<LogicValue>, swizzle it together instead.Logic.valueInt and Logic.valueBigInt; instead use equivalent functions on Logic.value.bit on both LogicValue and Logic; instead just check width.LogicValue.toString to decide whether or not to include the width annotation through includeWidth argument.LogicValues (https://github.com/intel/rohd/issues/90).bin (https://github.com/intel/rohd/issues/56).getRange and reversed on Logic and slice on LogicValue to improve consistency.slice in reverse-index order now reverses the order.zeroExtend and signExtend) on both Logic and LogicValue (https://github.com/intel/rohd/issues/101).IfBlock.withSet on LogicValue and Logic to make it easier to assign subsets of signals and values (https://github.com/intel/rohd/issues/101).Modules and their corresponding generated outputs.Deprecated swizzle and rswizzle global functions and replaced them with extensions on Lists of certain types including Logic, LogicValue, and LogicVal…
Iterable.forEach to make debug easier.ofBool to LogicValue and LogicValues (https://github.com/intel/rohd/issues/34).Interface API so that getPorts returns a Map from port names to Logic signals instead of just a list, which makes it easier to work with when names are uniquified.setPort from Interface. Use setPorts instead.swizzle and rswizzle global functions and replaced them with extensions on Lists of certain types including Logic, LogicValue, and LogicValues (https://github.com/intel/rohd/issues/70).ExternalModule to ExternalSystemVerilogModule since it is specifically for SystemVerilog.topModuleName a required named parameter in ExternalSystemVerilogModule to reduce confusion.simulationHasEnded bool to Simulator.Simulator to allow for injected actions to return Futures which will be awaited.Simulator warns about maximum simulation time when not appropriate.ExternalSystemVerilogModule could enter infinite recursion.SimCompare to properly check values at the end of a tick and support a wider variety of values in Vectors.Sequential signal sampling where under certain scenarios, signals would pass through instead of being flopped (https://github.com/intel/rohd/issues/79).from functions and replaced them with of to more closely follow Dart conventions (https://github.com/intel/rohd/issues/72).Renamed FF to Sequential (marked FF as deprecated) (breaking: removed clk signal)
LogicValues to improve performanceFF to Sequential (marked FF as deprecated) (breaking: removed clk signal)Sequential.multi for multi-edge-triggered blocks (https://github.com/intel/rohd/issues/42)Fix Interface.connectIO bug when no tags specified ( )
Interface.connectIO bug when no tags specified (https://github.com/intel/rohd/issues/38)Interface.getPorts bug (https://github.com/intel/rohd/issues/59)The first formally versioned release of ROHD.
Your coding agent can read these notes before it upgrades. Set up the MCP server →