rohd_hcl

What's Changed

• update deployment workflow to install SystemVerilog to Verilog conver… by @desmonddak in #224
• updated broken html links in markdown by @desmonddak in #226
• fix just the deprecated Port calls to Logic.port by @desmonddak in #231
• migrated to new Yosys and removed sv2v by @desmonddak in #229
• Multiplier doc by @desmonddak in #219
• Serializer doc link by @desmonddak in #220
• fix proper quotations of classes and literals true and false by @desmonddak in #223
• fix for MAC trace error by @desmonddak in #240
• bug in DAZ computing effectiveSubtraction incorrectly by @desmonddak in #239
• add definitionName to all components and update configurator/markdown… by @desmonddak in #227
• Fix signal names by @desmonddak in #237
• fix count internal naming by @desmonddak in #244
• update Interface classes to include the required clone() method. by @desmonddak in #245
• convert a boolean signExtend to a runtime or static parameter by @desmonddak in #246
• dot-product-component by @desmonddak in #243
• Resettable entries by @mkorbel1 in #253
• Enable Fifo to return the same type as was received by @mkorbel1 in #254
• Floating Point Value operations: negation and comparison by @desmonddak in #232
• changelog entries for 0.2.1 release by @desmonddak in #261

Full Changelog: v0.2.0...v0.2.1

• New Components:
  • Added an integer DotProduct component (https://github.com/intel/rohd-hcl/pull/243).
  • Added a ResettableEntries capability allowing us to initialize memories (https://github.com/intel/rohd-hcl/pull/253).
  • Added a new value type, SignMagnitudeValue, to use in testing (https://github.com/intel/rohd-hcl/pull/232/) and potentially for components.
• Added constraint generation to random() for FixedPointValuePopulator and FloatingPointValuePopulator which allows for generating random values in those types constrained by a fixed range, inclusive or exclusive (gte, gt, lt, lte), and in the case of FloatingPointValue, normal or subnormal numbers in that range (https://github.com/intel/rohd-hcl/pull/232/).
• Improved SystemVerilog output:
  • Improved default Module definition and instance naming throughout (https://github.com/intel/rohd-hcl/pull/227).
  • Improved output of SystemVerilog internal signal names throughout (https://github.com/intel/rohd-hcl/pull/237, https://github.com/intel/rohd-hcl/pull/244).
• Added FixedPointValue and FloatingPointValue operators including negation, and comparison.
  • For FixedPointValue this is a deprecating change as previous operators returned LogicValue and their future operators will return bool (https://github.com/intel/rohd-hcl/pull/232/). For now, bool return methods are provided for transitioning: .ltBool, .lteBool, .gtBool, and .gteBool. They will be deprecated in the future for operator <, operator <=, operator > and operator >=, respectively.
• Added dynamic sign extension capability to ReductionTree (https://github.com/intel/rohd-hcl/pull/246/).
• Bug fixes:
  • Fixed bug (https://github.com/intel/rohd-hcl/issues/239) denormals-as-zero (DAZ) support when computing effective subtraction in floating point addition.
  • Fixed build failure (https://github.com/intel/rohd-hcl/issues/240) in MultiplyAccumulate.
• Updates for current ROHD version 0.6.6 (https://github.com/intel/rohd/releases/tag/v0.6.6) compatibility:
  • Updated FIFO to return the LogicType instead of just Logic (https://github.com/intel/rohd-hcl/pull/254), leveraging ROHD 0.6.6's addTypedInput and addTypedOutput capabilities.
  • Fixed use of deprecated Port (https://github.com/intel/rohd-hcl/pull/231), which is now Logic.port in ROHD.
  • Updated implementations of Interface classes to add the required clone() method (https://github.com/intel/rohd-hcl/pull/245)
• Improved internal code documentation to use more references of types (https://github.com/intel/rohd-hcl/pull/223).

What's Changed

• Update default permissions, and update description by @mkorbel1 in #67
• Ready/Valid BFM by @mkorbel1 in #69
• Fix FifoChecker sampling bugs by @mkorbel1 in #70
• Fix memory model handling of different edge and latency situations by @mkorbel1 in #71
• More fixes to the memory model by @mkorbel1 in #72
• Hamming ECC by @mkorbel1 in #74
• Edge Detector by @mkorbel1 in #75
• migrate parallel_prefix to new branch by @desmonddak in #77
• Find Configurator by @mkorbel1 in #78
• Flutter experiment by @desmonddak in #79
• Update analysis options and doc checks for Dart 3.3.0 by @mkorbel1 in #80
• Fix documentation generation by @mkorbel1 in #81
• Gray Binary Converter by @quekyj in #54
• parallel prefix documentation updates by @desmonddak in #82
• schematic only changes by @desmonddak in #84
• Integer by @desmonddak in #85
• Add tests that configurator modules build by @mkorbel1 in #88
• Integer divider by @kimmeljo in #87
• Sum and Counter by @mkorbel1 in #89
• Clean serialization by @desmonddak in #92
• Extrema Component by @robtorx in #93
• Floatingpoint by @desmonddak in #97
• Enhancements for modifying and printing partial product arrays. by @desmonddak in #102
• Add CompoundAdder component by @aasorokiin in #98
• Shift Register Updates by @robtorx in #105
• Fpadder by @desmonddak in #106
• Pp array by @desmonddak in #107
• Clock gating by @mkorbel1 in #96
• Fixed Point Value system by @soneryaldiz in #99
• Refactoring of FloatingPointValue constructors for ease of use and extension by @mkorbel1 in #110
• Multi Cycle Divider Enhancements: remainder output and isSigned input by @kimmeljo in #117
• Fixed Point Logic and Fixed Point to Floating Point Conversion by @soneryaldiz in #116
• Floating Point to Fixed Point Converter Module by @soneryaldiz in #123
• Flop compressor by @desmonddak in #118
• Agnostic multiplier by @desmonddak in #125
• Pipeline FP Adder by @desmonddak in #126
• Fpvaluecompare by @desmonddak in #131
• bug fix for fp8e4m3 by @desmonddak in #132
• Fpfixes by @desmonddak in #134
• fix signed operand mode in multiplier, added pipelining by @desmonddak in #137
• Bug fix for pipelined multiplication signals by @desmonddak in #138
• [MultiCycleDivider] Bug Fixes for Large Operands and Ready Indication Polarity by @kimmeljo in #129
• Gated counter and toggle gate by @mkorbel1 in #111
• [MultiCycleDivider] Patch of prior bug fix to properly support unsigned division by @kimmeljo in #141
• Full set of sign variants (signed/unsigned/selected) for multiplier operands by @desmonddak in #144
• remove redundant assignment statement in fpadder by @desmonddak in #145
• adder api and documentation cleanup by @desmonddak in #147
• Compatibility with ROHD v0.6.0, plus some minor fixes by @mkorbel1 in #150
• Extensive fp cleanup, support Inf/NaN, addition of simple fp multiplier by @desmonddak in #152
• Refactor signextend by @desmonddak in #154
• Naming fp by @desmonddak in #156
• Generic CSR Functionality by @kimmeljo in #151
• Naming definition by @desmonddak in #160
• bypass link check and flutter bug for now by @desmonddak in #164
• Bypass flutterbug by @desmonddak in #165
• FloatingPointConverter by @desmonddak in #161
• Tree component by @desmonddak in #155
• rounding and fixed point fixes by @desmonddak in #167
• Fixed lossy by @desmonddak in #172
• FloatingPointValue refactor for simpler resuable construction by @mkorbel1 in #175
• faster priority encoder by @desmonddak in #178
• Allowing CSR Width to Exceed Frontdoor Interface Data Width by @kimmeljo in #177
• Improve MemoryStorage read and add dump for verilog-compliant memory files by @mkorbel1 in #176
• FloatingPointUtilities extraction for swap/sort, and parameterization of some FP components by @mkorbel1 in #182
• Serial Peripheral Interface by @robtorx in #148
• Compound adder by @desmonddak in #179
• Add Find N'th Pattern component by @izzianyramli in #187
• Floating Point Square Root Module with Variable Odd Mantissa and No Rounding by @lucasphillips in #188
• Fix bug in SparseMemoryStorage where reloading the same data corrupted the first byte by @mkorbel1 in #195
• Reduction module by @desmonddak in #180
• Fix lint issues for Dart 3.8 by @mkorbel1 in #202
• Fixing bug in CsrTop frontdoor reads by @kimmeljo in #197
• Optional front-door access for CSRs, plus immutable configuration refactoring by @mkorbel1 in #205
• Explicit JBit fpadder and components by @desmonddak in #193
• Add error generation to TreeOneHotToBinary by @mkorbel1 in #211
• FixedPoint is now a LogicStructure with a Populator by @desmonddak in #208
• AXI4 Interface and Functional Modeling by @kimmeljo in #159
• reduction with control working by @desmonddak in #204
• Runtime configuration using dynamic by @desmonddak in #214
• Widen the confapp sidebar to allow for names to be displayed properly by @desmonddak in #216
• AXI4 Subordinate BFM bug fix for tight consecutive write/read by @kimmeljo in #217
• Denormal as Zero / Flush to Zero feature added to floating-point adders by @desmonddak in #212
• change radix to a named arg for multipliers by @desmonddak in #218
• Prepare for 0.2.0 release by @desmonddak in #215

New Contributors

• @kimmeljo made their first contribution in #87
• @robtorx made their first contribution in #93
• @aasorokiin made their first contribution in #98
• @soneryaldiz made their first contribution in #99
• @izzianyramli made their first contribution in #187
• @lucasphillips made their first contribution in #188

Full Changelog: v0.1.0...v0.2.0

• Added extensive variable-width floating-point support:
  • Added support classes FloatingPointLogic and FloatingPointValue (https://github.com/intel/rohd-hcl/pull/97), (https://github.com/intel/rohd-hcl/pull/110), (https://github.com/intel/rohd-hcl/pull/131), (https://github.com/intel/rohd-hcl/pull/156), (https://github.com/intel/rohd-hcl/pull/175), (https://github.com/intel/rohd-hcl/pull/134).
  • Added FloatingPointAdder abstract component API with implementations FloatingPointSinglePathAdder and FloatingPointDualPathAdder (https://github.com/intel/rohd-hcl/pull/106), with pipelining (https://github.com/intel/rohd-hcl/pull/126), (https://github.com/intel/rohd-hcl/pull/182).
  • Added explicit J-Bit option for FloatingPointValue and FloatingPointLogic (https://github.com/intel/rohd-hcl/pull/193) as well as in the FloatingPointAdderSinglePath and FloatingPointAdderDualPath. This allows for unnormalized floating-point representation by storing the leading '1' or j-bit in the mantissa.
  • Modified FloatingPointValue and FloatingPointLogic to support denormal-as-zero (DAZ) and flush-to-zero (FTZ) (https://github.com/intel/rohd-hcl/pull/212/). Implemented in FloatingPointAdderSinglePath and FloatingPointAdderDualPath.
  • Added FloatingPointConverter component (https://github.com/intel/rohd-hcl/pull/123), (https://github.com/intel/rohd-hcl/pull/161) to convert between different widths of FloatingPointLogic.
  • Added FloatingPointMultipler base API with FloatingPointMultiplierSimple implementation component (https://github.com/intel/rohd-hcl/pull/152), (https://github.com/intel/rohd-hcl/pull/160).
  • Added square root components for floating-point (https://github.com/intel/rohd-hcl/pull/188).
• Added fixed-point support classes FixedPointLogic and FixedPointValue (https://github.com/intel/rohd-hcl/pull/99), (https://github.com/intel/rohd-hcl/pull/132), (https://github.com/intel/rohd-hcl/pull/167), (https://github.com/intel/rohd-hcl/pull/172), (https://github.com/intel/rohd-hcl/pull/208).
• Added StaticOrRuntimeParameter configuration class which provides API support for configuration of a hardware feature within a component using a single parameter for either static configuration with a bool or dynamic configuration with a Logic signal (https://github.com/intel/rohd-hcl/pull/214).
• Added AXI4 interface with functional model (https://github.com/intel/rohd-hcl/pull/159).
• Added Control Status Register capabilities (https://github.com/intel/rohd-hcl/pull/151), (https://github.com/intel/rohd-hcl/pull/205), (https://github.com/intel/rohd-hcl/pull/197).
• Added Sum and Counter components (https://github.com/intel/rohd-hcl/pull/89) which are fully-featured capabilities to track counters with multiple inputs and various options to handle overflow.
• Added Serializer and Deserializer components (https://github.com/intel/rohd-hcl/pull/92) which handle marshalling and unmarshalling of data onto wider or narrower interfaces.
• Added ReductionTree module and ReductionTreeGenerator component (https://github.com/intel/rohd-hcl/pull/155), (https://github.com/intel/rohd-hcl/pull/180), (https://github.com/intel/rohd-hcl/pull/204) which allow generalized reduction operations of arbitrary radix with pipelining.
• Added Extrema component (https://github.com/intel/rohd-hcl/pull/93).
• Added clock gating componentry (https://github.com/intel/rohd-hcl/pull/96), (https://github.com/intel/rohd-hcl/pull/111).
• Added fast RecursiveModulePriorityEncoder (https://github.com/intel/rohd-hcl/pull/178) to complement ParallelPrefixPriorityEncoder.
• Added OnesComplementAdder component (https://github.com/intel/rohd-hcl/pull/85).
• Added CompoundAdder and CarrySelectOnesComplement adder components (https://github.com/intel/rohd-hcl/pull/98), (https://github.com/intel/rohd-hcl/pull/178).
• Added extensive integer multiplication support:
  • Added multiplier componentry such as parameterizable Booth-encoders, different kinds of sign extension on a partial-product array, delay-driven Wallace tree compression, and selection of differnt kinds for final adders (https://github.com/intel/rohd-hcl/pull/85).
    • Added special visualization of partial-product arrays for debug (https://github.com/intel/rohd-hcl/pull/102), (https://github.com/intel/rohd-hcl/pull/107).
    • Added support for pipelining (https://github.com/intel/rohd-hcl/pull/118), (https://github.com/intel/rohd-hcl/pull/137), (https://github.com/intel/rohd-hcl/pull/138).
    • Added support for rectangular multiplication and multiple kinds of sign extension (https://github.com/intel/rohd-hcl/pull/154).
  • Added components CompressionTreeMultiplier and CompressionTreeMultiplyAccumulate supporting signed and unsigned operands, both statically and logically controlled, rectangular multiplication, Booth encoding with radices 2,4,8, and 16, delay-driven Wallace tree, and configurable final adder, all with exhaustive narrow-width testing (https://github.com/intel/rohd-hcl/pull/144).
  • Added wrapper class NativeMultiplier (https://github.com/intel/rohd-hcl/pull/125).
• Added integer MultiCycleDivider (https://github.com/intel/rohd-hcl/pull/87), (https://github.com/intel/rohd-hcl/pull/117), (https://github.com/intel/rohd-hcl/pull/129), (https://github.com/intel/rohd-hcl/pull/141).
• Added Parallel Prefix Tree components: adding ParallelPrefixAdder, ParallelPrefixEncoder, ParallelPrefixIncr, ParallelPrefixDecr and ParallelPrefixOrScan (https://github.com/intel/rohd-hcl/pull/77), fixing Issue (https://github.com/intel/rohd-hcl/issues/12). The types of prefix trees supported are Kogge-Stone, Sklansky, Brent-Kung, and Ripple.
• Added Ready-Valid Bus Functional Model (https://github.com/intel/rohd-hcl/pull/69).
• Added HammingEccTramsitter and HammingEccReceiver componentry with SECC/SEDDED/SECDED, and SEDDEDTED (https://github.com/intel/rohd-hcl/pull/74).
• Added BinaryToGray and GrayToBinary conversion components (https://github.com/intel/rohd-hcl/pull/54).
• Added EdgeDetector component (https://github.com/intel/rohd-hcl/pull/75).
• Added Serial Peripheral Interface componentry and functional modeling (https://github.com/intel/rohd-hcl/pull/148).
• Added Find-Nth component (https://github.com/intel/rohd-hcl/pull/187).
• Modified ShiftRegister component to support async reset and different stage reset values (https://github.com/intel/rohd-hcl/pull/105).
• Modified tree form of OneHotToBinary to add error generation (https://github.com/intel/rohd-hcl/pull/211).
• Fixed bugs in FifoChecker sampling at clock edges that caused failures. (https://github.com/intel/rohd-hcl/pull/70).
• Updated ApbTracker for configurable widths and data (https://github.com/intel/rohd-hcl/pull/71).
• Breaking: ParityTransmitter deprecates parity for code,checkError for error and originalData for data.
• Fixed memory model for read-after-write or read on non-zero latency (https://github.com/intel/rohd-hcl/pull/72).
• Fixed bug in SparseMemoryStorage (https://github.com/intel/rohd-hcl/pull/195).
• Improved MemoryStorage read (https://github.com/intel/rohd-hcl/pull/176).
• Added online schematic generation in the web generator application using yoWASP (WebAssembly form of the yosys logic synthesis tool) and d3schematics graphics (SVG) generation (https://github.com/intel/rohd-hcl/pull/84).
• Modified code to be compatible with ROHD 0.6.0 (https://github.com/intel/rohd-hcl/pull/150).
• Modified code to be lint-compatible with Dart 3.8 (https://github.com/intel/rohd-hcl/pull/202).
• Updated flutter to version 3.27.0 (https://github.com/intel/rohd-hcl/pull/212/).
• Added flutter to devcontainer (https://github.com/intel/rohd-hcl/pull/79).
• Fixed documentation linting to be compatible with Dart 3.3.0 and above (https://github.com/intel/rohd-hcl/pull/80).

The first formally versioned release of ROHD-HCL. Deployed to https://pub.dev/packages/rohd_hcl

• The first formally versioned release of ROHD-HCL.