github.com/zhoushoujianwork/easyeda-agent

自 0.8.3 以来的整体收口版本:PCB 布线/DRC 从「能放」走到「能连、能查、能救」, 原理图从零建图闭环幂等化,并沉淀了「抄官方板 → 自主设计」的训练方法论与 ADR-0002 前置设计交互。以下按主题汇总 0.8.4–0.8.13 各 dev 迭代的用户可见变化 (逐条明细见下方各历史条目)。

Added

• PCB 布线手术刀 + 换层跳线:pcb.route.delete(按 primitiveId 精准删 track/arc/via,rip_up 不再整网重铺)、pcb.route.via_hop(入口 stub→via→对层 track→via→出口 stub 的复合换层,默认两层各放同网键合 fill 桥接 track↔via 裸结点)、 pcb.route.route_short 多层布线(长/跨层 hop 用 via 换层,不再全推迷宫档)。
• headless DRC 盲区补齐:pcb check 新增通用间距规则(抓导线短接)、via-bond (ERROR:track↔via 裸结点未被键合 fill 覆盖)、floating-track-island、dangling-end (面积锚定)、缝合过孔间距、挖槽/过孔间距感知;pcb drc 支持 --json/--timeout
  • daemon 侧防重入。DRC 实测 66→31、Connection 9→0。
• 单网内电层:同一 GND 网可独占内电层填充(via-stitch → pour)。
• 原理图分组与断连:sch group-move(器件+周边 stub 导线/flag 刚性整体平移, 无状态虚拟分组)、schematic.pin.disconnect 支持 pinX+pinY 坐标定位。
• sch autoplace-free:零区域自动布局,把件塞进纸面空白处。
• 标准器件库扩充:芯片级设计 11 件 + case001 通用料 24 件(references/standard-parts.json)。
• pcb.silk.label_pads 新增 alignAxis / --align-axis 参数:可选择按 X 轴或 Y 轴贴齐标注(x/y/auto),并在结果中返回 align_axis_chosen。适合排针/连接器 等不同朝向封装,让丝印标注沿焊盘阵列形成整齐队列。

Changed

• sch autoconnect 幂等化(issue #50):components.list --include-pins 的每个 pin 附带权威网表来源的 net 字段,autoconnect 据此三态判定 pin 是否已连目标网, 重跑不再叠加 flag。
• Skill 方法论沉淀:ADR-0002 前置设计方案书(S0)+ 三档交互模式(决策交互化、 执行自动化);紧凑布局设为默认 + 手工修线三律;官方板对标 §7.8–7.9 地策略选择判据 (单 GND→双 PLANE;多地域→全 SIGNAL 分区 pour);抄图训练闭环(XDS110 174/174 pin 一致 + 多页拆分)固化为验收方法。

Fixed

• sch page.rename 写后自校验(issue #55):改名后 doc ls 读到旧页名 → 短间隔 重试读回确认,命中 verified:true,超时如实返回 verified:false+warning。
• --all-pages 非激活页壳数据告警(issue #54):sch read/list/check/layout-lint 对非激活页如实警告 pins/bbox 可能为空,layout-lint 把 skip 升为醒目 WARN。
• sch check geom-net-mismatch 对 netflag/netport 静音:designator 为空的原语 网表交叉校验静音,几何单独判(64/64 误报→0)。
• sch autolayout 锚点 snap 到 5 网格:分区居中产出的分数坐标(206.25)不再致 connect_pin 批量失败;connect_pin 引脚离网格时快速失败给可行动报错。
• lib search 对 LCSC C 号精确匹配:不再模糊命中错料。

Typed PCB layer/view switching for bottom-side visual QA (#40) + release-flow ClawHub integration. Connector code changed (extension/src/actions.ts) — this release requires a connector re-import (uninstall old → import new .eext → fully quit & relaunch EasyEDA). Version 0.8.2 is skipped: it was burned on ClawHub by a stale-content skill upload (clawhub workdir trap; versions are immutable there), so 0.8.3 keeps CLI/connector/skill aligned.

Added

• Typed PCB layer/view actions (no more manual UI clicks for bottom-side checks): pcb.layers.set_current (pcb layer-set, accepts id|name|top|bottom|inner1), pcb.layers.visibility (pcb layer-visibility, presets top-only|bottom-only|copper-only|silk-only or explicit show/hide), pcb.view.side (pcb view-side) — selects the side's copper and focuses its copper/silk layers so the next snapshot reflects that side. No native canvas flip API exists, so view-side is a layer-focus approximation, not a physical board flip.
• make release now publishes the skill to ClawHub at the same version (best-effort — a hub failure doesn't block the release; retry with make publish-skill VERSION=…). Uses an absolute path to dodge the clawhub global-workdir trap.

Fixed

• currentLayer:null readback (#40) — pcb.layers.list now activates the PCB tab before getCurrentLayer and returns visibleLayers as display-state evidence when currentLayer is empty.
• README install commands — removed the non-working skillhub.cn CLI command (web-only community, no /api/cli/v1 endpoint); ClawHub + GitHub Release skills.tar.gz are the supported skill-install paths.

Fresh-PCB pour-reflow fix, solidified end to end (root cause pinned → commands → playbook → fresh-board replay-verified: DRC 55 → 1). Go/CLI only — no connector code change, no re-import needed.

Root cause pinned: a PCB document created in the current session and never reloaded computes pour reflow from a creation-time rules snapshot — rule writes (readback shows them), pour-rebuild, and tab-switching have NO effect until the document is really closed and reopened; already-reloaded documents honor rule writes immediately. On top of that, the fresh-board reflow runs ~3% under the configured clearance (10mil → ~9.7mil) and skips thermal spokes (suspected platform issue, to be reported upstream).

Added

• easyeda doc reload [name|uuid] — save + close + reopen a document (a real reload; doc switch only changes the foreground tab). Refreshes the per-document reflow rules snapshot; run pcb pour-rebuild after reloading a PCB. Saves first (typed schematic.save/pcb.save by document type), so no edits are lost.
• easyeda pcb drc-rules-set --pour-clearance <mil> — the write side of drc-rules (v1 knob: pour/plane copper clearance, raise-only — never loosens a stricter board). Patches Plane lineClearance (copperRegion both pad models + innerPlane) of the current rule configuration, writes it back (bare-config API shape — the {name, config} wrapper silently no-ops), verifies by re-read; a write on a system preset turns it into a per-board 自定义配置 copy, as the platform requires.
• esp32-mini playbook: rules-pour-margin + reload-pcb + pour-rebuild-2 steps (182→186) — margin 10→12mil before pouring, then a document reload + second rebuild after, so a replay on a freshly created PCB passes DRC directly. Verified end to end on a fresh board (ceshi/Board4): 47 + 186 steps green, official DRC = 1 (the known #33 add-component netlist false positive).

Recording/demo-mode reliability — a one-call stage capture that gates on the frame, plus blank-frame detection — and a netless-pour cleanup, on top of the accumulated connector fixes.

Added

• easyeda pcb stage-snapshot --stage "…" — one-call recording/demo STAGE capture: native PCB snapshot + a data bundle (components/tracks/vias/pours/nets/drc)
  • a stage.json manifest, GATED on the frame — a BLANK / STALE / wrong-document (foreground tab not a PCB) capture exits non-zero, so a set -e recording script halts instead of banking a bad frame. Go/CLI only, no re-import.
• Blank-frame detection on pcb/sch snapshot. The capture reads the FOREGROUND tab's rendered canvas, which comes back BLANK when the window isn't visibly rendering (minimized / backgrounded). The CLI decodes the PNG and WARNs on a blank frame — distinct from a STALE (byte-identical) one. Verified: no API call (view fit / zoom / ratline / openDocument / tab-switch) repaints a hidden window; the only fix is bringing EasyEDA to the foreground. Go/CLI only.
• easyeda pcb pour-clean --netless [--dry-run] — remove copper pours bound to no net (dead copper that pour-fit --replace can't clear — it only matches same-net pours). Surfaced by the new pcb check netless-pour rule. Go/CLI only. (#34)
• easyeda debug exec --timeout <sec> — override the 20s round-trip default for slow eda.* calls (e.g. sch_Netlist.getNetlist(), which can loop >90s on a schematic with floating pins — prefer getNetlistFile(), which sch read uses and never hangs). Go/CLI only, no re-import.

Fixed

• connect_pin/sch autoconnect now actually FORM the net (grid-snap fix). The stub endpoint (grid-aligned pin + a non-grid offset like 18 → 338) landed off the 10-unit schematic grid, but a created netflag/netport SNAPS to the nearest grid point (340) — so the stub ended a grid-step short of the flag's connection pin, the flag floated unconnected, its net NAME never applied, and same-named flags NEVER merged (every pin became its own auto-named 1-pin net $1N…). connect_pin now snaps its stub endpoint to the grid so it coincides with the snapped flag pin. Verified: two --net MERGE netports now read back as one net MERGE deg 2 [R1.2, R2.1] (was two $1N singletons). Unblocks building a netlisted schematic from scratch via the API. (Re-import needed.)
• pcb.pour.create refuses a netless pour. An empty/absent net used to be silently coerced to '', creating dead copper (a net:"" pour) that pour-fit --replace can't clear — the #34 confusion. It now errors net is required. The CLI (pcb pour / pour-fit) already fails fast; this is the connector-side backstop for raw debug.exec_js / other callers. (Takes effect after re-importing the connector.)
• pcb new-board no longer silently steals the schematic. A schematic can belong to only ONE Board in EasyEDA Pro, so createBoard(schematicUuid) on an already-bound schematic moves it into the new board — leaving the old board with just its PCB ("原理图没了"). board.new_pcb now detects an already-bound schematic and refuses with a clear error naming the owning board; pass --force (force: true) to move it deliberately.
• board list / pcb board-info no longer crash on a PCB-only or schematic-only Board. serializeBoard read board.schematic.uuid / board.pcb.uuid unconditionally, throwing Cannot read properties of undefined (reading 'uuid') for any board missing one side (exactly the orphaned boards the old new-board produced). It now emits null for the missing side.

The market-ready PCB pass since v0.6.0 — a reconstructed PCB DFM audit (pcb check), a full silkscreen suite, the verified 4-layer inner-plane recipe, and a reconnect UX fix. (Consolidates the dev-loop releases 0.6.1–0.6.7 below.)

Added

• pcb check — reconstructed DFM audit (the PCB sibling of sch check; catches the design-for-manufacture problems the native pcb drc clearance check does NOT flag). Copper rules compute purely Go-side from placed copper and never mutate: dangling-end (a track end anchored to nothing → floating copper), acute-angle (same-net segments bending <90° → acid trap), non-orthogonal (a track off the 0/45/90° grid → free-angle routing), track-over-pad (a track crossing a pad it doesn't terminate on: cross-net = ERROR short), overlapping-via / single-layer-via, width-mismatch, duplicate-segment, and 3W parallel-coupling; plus silkscreen-flipped (a designator on the wrong silk layer / mirrored / non-upright) and per-layer antenna-keepout (an antenna module lacking a no-copper keep-out on every copper layer). --strict exits non-zero on any WARN/ERROR (gate-able).
• Silkscreen suite — pcb silk-add (a FREE silkscreen string: board credit / LED +/− polarity marks; configurable layer/font/stroke/rotation, JLCPCB-legible defaults), pcb silk-set (batch-adjust existing silk + an align-to-reference shortcut: center a board credit, align a label to a component/board/fill edge), and the read handlers pcb.silk.list (text layer/mirror/reverse/rotation) + pcb.region.list bbox that feed the DFM checks.
• easyeda pcb new-board (board.new_pcb) — create a brand-new board (板) with a fresh EMPTY PCB page bound to a schematic (CLI equivalent of the UI 新建PCB / 原理图转PCB), then pcb import-changes to lay it out from scratch. Distinct from board.create (link-only). Runs the required 2-step SDK sequence that is otherwise a silent no-op — createBoard(schematicUuid) mints a board shell, then createPcb(boardName) adds the PCB INTO it — with shell rollback on failure. --schematic defaults to the current board's schematic.
• easyeda notify (system.notify) — show a non-blocking toast INSIDE the EasyEDA window so the design flow can announce each stage live ("完成 布线,下一步 铺铜"). --type info|success|warn|error|question, --duration.

Changed

• pcb silk-align → position-aware (v2) — ranks each designator's 4 sides by local free space + board position + a crowd-axis bonus, and avoids other parts' pads, bodies, keep-out regions, the board outline (now resolves rounded/polyline outlines), and other labels; keeps assembly clearance around each footprint (--spacing); a boxed-in part is reported (unresolved), never shoved onto a pad.
• pcb power-planes flips the GND inner layer to 内电层/PLANE after pouring (verified pour-while-SIGNAL → flip-type → rebuild recipe, DRC clean), matching the common customer stackup GND=内电层 / VCC=信号层. Drove the ESP32 regression board DRC 31→0, No-Connection→0.
• pcb auto-place --assembly-gap (default 40 mil) floors the chip-to-satellite gap at a hand-SOLDER clearance, not just the DRC routing clearance (~28 mil packed too tight to reach with an iron). pcb check antenna-keepout now recognizes a single MULTI-layer(12) region as covering every copper layer — one 多层 keep-out replaces the per-layer set. design-flow.md PCB pipeline reordered so keep-out regions + silk-align run BEFORE routing (post-hoc keep-outs forced re-routing).

Fixed

• Reconnect toast dedup — one toast per daemon outage instead of one on every 3s retry (they were stacking and covering UI options during an outage).

Docs

• README split into a Chinese homepage (README.md) + English (README.en.md); new demo recording storyboard docs/demo-storyboard-esp32-mini.md; FEATURES action count 85→88; official-marketplace coverage survey (docs/marketplace-coverage.md).

PCB automation milestone (tasks #21–#32). Connector-side changes below; the bulk of the release is DAEMON-side (Go CLI) PCB automation, summarized under "Daemon".

Added

• pcb.silk.align (task #30) — reposition each component's DESIGNATOR silkscreen with COLLISION AVOIDANCE: searches candidate slots around each footprint (preferred side first, then other directions at increasing distance) and takes the first that hits no other component body and no already-placed label — dense-cluster designators get pushed into open space instead of piling up. The designator is a component-bound attribute (pcb_PrimitiveString is empty), repositioned via pcb_PrimitiveAttribute.getAllPrimitiveId(componentId) + .modify(id,{x,y}). Reports unresolvedCollisions. CLI: pcb silk-align.
• pcb.stackup.set (task #26) — configure the board stackup: set the copper layer count (2/4/6/…/32 via setTheNumberOfCopperLayers) and/or set inner layers' type SIGNAL↔PLANE (内电层, via modifyLayer). A PLANE inner layer gives GND/power a dedicated plane on 4+ layer boards — the clean fix for the 2-layer pour conflict where two power nets can't both connect on one shared layer. Read via pcb.layers.list. CLI: pcb stackup set --layers 4 --plane 15 --plane 16.

Fixed

• Connector auto-reconnect wedge (需要重开窗口才恢复) — after a daemon restart (dev hot-reload) or a long window-backgrounding, isConnecting could leak true and freeze EVERY reconnect path at once: the watchdog tick, the port scan, AND the focus/online/visibility wake listeners all early-returned on isConnecting, so only fully reopening the EasyEDA window recovered. Now (1) the watchdog force-resets a connect flow still unsettled after ~24s (STUCK_CONNECTING_TICKS), and (2) the foreground/online wake forces a clean reconnect through a stuck isConnecting (cancelConnectionFlow() first) instead of being blocked by it.

Daemon (CLI) — PCB automation pass

All real-machine verified on the ESP32 regression board; each easyeda pcb … subcommand:

• Rule-aware route-short / auto-place / pour — read the board's live DRC rule (pcb drc-rules) and conform (widths/clearance/via/copper-to-edge) instead of hardcoding; fall back to a canonical JLCPCB fab-rule reference (real per-board-type exports). (#22/#32)
• route-short v2: obstacle-aware L-orientation, and skips power/ground nets by default (they belong in a pour — routing 3V3 as thin tracks was the #1 DRC source). (#23)
• pcb outline-fit (tighten to parts) / pcb outline-round (rounded-rect outline). (#21/#29)
• pcb layout-lint — placement quality + routability score (ratsnest MST + crossings). (#25)
• pcb power-planes — 4-layer power distribution: GND + power on dedicated inner planes
  • via-stitch each pad (drove the regression board's No-Connection to 0). (#26)
• pcb region / fill / slot — antenna keep-out (禁铺铜) & board cutout (挖槽). (#28)
• Confirmed platform walls (no eda.* API): teardrops, controlled-impedance, interactive routing.

Added

• pcb.add_component (task #20) — add ONE part to an EXISTING PCB and wire it, the working alternative to pcb.import_changes (which is a no-op for API-added parts). Places the footprint (pcb_PrimitiveComponent.create), links it to its schematic twin (uniqueId + designator), assigns each pad's net from a caller- supplied nets map (pcb_PrimitivePad.modify — the step that actually wires it, since net→pad assignment is otherwise part of the broken import flow), and recomputes ratlines. CLI: easyeda pcb add-component. schematic.read now also returns each component's uniqueId (the sch↔PCB link key to pass in).

Investigated

• eda.pcb_Document.importChanges does NOT sync API-added components to an existing PCB (returns true, count unchanged) — root-caused to incremental-add being a platform no-op; superseded by pcb.add_component.

Added

• PCB routing roadmap R1 (copper pour) + R2 (rip-up/list) from docs/ecosystem-survey.md §7 — 8 new actions, d.ts-grounded + adversarially reviewed:
  • pcb.pour.create / pcb.pour.list / pcb.pour.delete / pcb.pour.rebuild — copper pour (铺铜). create takes raw points; the connector builds the IPCB_Polygon via pcb_MathPolygon.createPolygon (the missing piece behind the old "无法创建覆铜边框图元" failures — you must pass a polygon object, not raw points), then rebuildCopperRegion() computes the fill. fill = solid|grid|grid45. CLI easyeda pcb pour / pour-list / pour-delete / pour-rebuild.
  • pcb.route.rip_up — reliable rip-up (getAll → filter → delete on stable primitive APIs, the official kirouting pattern). Deletes tracks+arcs+vias on copper layers only (TOP/BOTTOM/INNER) — never the board outline, silkscreen/assembly/mechanical artwork, or locked primitives. --net scopes; omit = all. CLI easyeda pcb rip-up.
  • pcb.line.list / pcb.via.list — read routed tracks/vias. CLI pcb track-list / pcb via-list.
  • pcb.clear_routing — wraps native clearRouting (@alpha, may be undefined; prefer pcb.route.rip_up). CLI easyeda pcb clear-routing.
  • Smart/interactive routing (single/multi/diff routing, stretch, optimize, length-tuning, fanout) has NO eda.* API — documented as a hard boundary (§7).
• Five actions absorbed from the official open-source extension ecosystem (see docs/ecosystem-survey.md), each grounded in pro-api-types signatures:
  • schematic.library.get_by_lcsc — resolve LCSC C-numbers directly to {libraryUuid, uuid} via eda.lib_Device.getByLcscIds (deterministic, no free-text ranking; reports notFound). CLI easyeda lib by-lcsc --lcsc C….
  • pcb.line.create — create a copper track via eda.pcb_PrimitiveLine.create (mutating). CLI easyeda pcb track.
  • pcb.via.create — place a via via eda.pcb_PrimitiveVia.create (mutating). CLI easyeda pcb via.
  • pcb.report — read-only design report (per-net length, net-class totals, differential-pair skew, equal-length spread) over eda.pcb_Net.getNetLength + eda.pcb_Drc.getAll{NetClasses,DifferentialPairs,EqualLengthNetGroups}. CLI easyeda pcb report.
  • pcb.drc.rules — read eda.pcb_Drc.getCurrentRuleConfiguration without running a check. CLI easyeda pcb drc-rules.
  • Live-verified on a real board (PCB1, connector 0.5.15): A1 resolves C6186→AMS1117-3.3 identity; A5 returns the full rule config; A3 reports 4 nets with length/net-class/diff/equal-length; A2 creates a GND track (net length read back 0→500, confirming it bound to the right net); pcb drc + save pass.
• pcb.save — save the active PCB to disk (eda.pcb_Document.save), the PCB counterpart to schematic.save. CLI easyeda pcb save. PCB autosave is now on: the daemon's debounced autosave fires pcb.save after a PCB-mutating action, closing the in-memory-edit data-loss gap that previously only schematic edits were protected from (saveActionForDocType now maps pcb→pcb.save).

Fixed

• pcb.outline.set now creates the REAL board-outline object (类型=板框), not loose lines. Root cause of "the outline vanished when I cleared routing" + "DRC doesn't flag out-of-board": the outline was drawn as N separate pcb_PrimitiveLines on layer 11. A loose line on the board-outline layer is just a wire that happens to sit there — EasyEDA does NOT treat it as the board boundary (DRC ignores it for enclosure, the UI "清除布线 / clear routing" deletes it). Compared a UI-drawn 板框 against ours: the real outline is ONE pcb_PrimitivePolyline whose polygon is an IPCB_Polygon. Fix: build the closed-polygon source [x0,y0,'L',…,x0,y0] → eda.pcb_MathPolygon.createPolygon → eda.pcb_PrimitivePolyline.create('', 11, polygon, lineWidth, /*lock*/true) — one locked polyline. pcb.outline.get/clear updated to read/delete the polyline (bbox from its rendered extent; legacy lines still handled). Default lineWidth 10mil. Returns outlineId. Create flow verified live (createPolygon + polyline produced a 类型=板框 object matching the UI's).
• view region + schematic.snapshot --no-fit now reliably captures the requested local region (issue #20). Three coordinated fixes: (1) the snapshot handler now waits for the canvas to repaint (two requestAnimationFrames with a timeout fallback) BEFORE reading the frame, so a preceding view region viewport has actually landed — previously --no-fit grabbed the pre-region frame because EasyEDA does not synchronously repaint after eda.* view calls (the --fit path only "worked" by accident, since zoomToAllPrimitives nudged a redraw). (2) Built-in stale-frame detection: the snapshot result now exposes the frame sha256; thread it back via sch snapshot --previous-sha256 <sha> and the connector detects a byte-identical (stale) frame, retries once after another redraw, and reports stale/staleRetry. (3) view.region now normalizes the rectangle (sorts each axis to min/max) and rejects a zero-area box, so a reversed/degenerate bound no longer renders as a tiny sliver in a blank frame; view region CLI help documents the y-DOWN schematic axis semantics and units.
• schematic.power.connect_pin (sch connect) --direction up/down no longer inverts the stub/netport endpoint. EasyEDA Pro schematic coords are y-DOWN (a larger stored y renders LOWER on screen, verified on 3.2.121, issue #19), but the endpoint math assumed y-UP, so --direction up pushed a top-pin stub DOWN into the IC body and --direction down pushed a bottom-pin stub UP — visually wrong even when DRC was clean. up now decreases y (visually higher) and down increases y (visually lower). The flag-rotation table is unchanged: it is calibrated against real rendered bbox and already keyed to visual directions, so the corrected endpoint and the flag orientation now agree (callers no longer need the --direction down --rotation 90 workaround to get a visually-upward netport).
• schematic.check no longer false-flags merged-stub endpoints as wire-over-pin, and floating-pin findings now carry component-level detail. A pin coincident with a wire endpoint or a netflag/netport/netlabel anchor is the legitimate terminus of its own sch connect stub; when EasyEDA auto-merges collinear touching stubs into one long wire an inner pin lands in that wire's interior and was wrongly reported as a through-pin short (the official DRC stays clean). Rule 3 now excludes pins that coincide with a wire vertex or a net-marker anchor. Floating-pin findings now include primitiveId and a pinDetails[] array (number, name, x, y) so the --json report identifies the component and pin without a second lookup; the text report prints the per-pin name + coordinates and falls back to primitiveId when the designator is empty.

Fixed

• schematic.pin.set_no_connect no longer reports a false success. On EasyEDA Pro 3.2.x, pin.setState_NoConnected is a no-op — the pin primitive has no noConnected field (verified by re-pull, DRC re-run, and a canvas snapshot: no 非连接标识 is ever placed and DRC still treats the pin as floating). The setter is typed @public, so the prior implementation compiled and returned ok while silently doing nothing. The handler now verifies the write and fails with EDA_CALL_FAILED, naming it as an EasyEDA platform limitation (not a connector defect) and returning notApplied[]. It auto-passes if a future build makes the setter real. There is no public eda.* API to place a 非连接标识 on this version — use schematic.check to enumerate floating pins.
• schematic.wire.create now normalizes nested points (issue #5). EDA's eda.sch_PrimitiveWire.create only accepts a flat number[] ([x1,y1,x2,y2,…]); a nested [[x,y],…] payload failed with EDA_CALL_FAILED / "create failed!". The connector now flattens nested points at a single source of truth (normalizeWirePoints in util.ts), so CLI / call / sch.py / debug.exec_js all accept either form. Also validates the list is an even-length (≥4) run of finite numbers. CLI sch wire --help and auto-layout-sop.md updated to document both forms.

Added

• schematic.check — reconstructed per-item design check + routing-quality rules. The EDA schematic DRC API (eda.sch_Drc.check) returns only an aggregate {count,type} and layout-lint only sees component bbox overlap; this fills both gaps by computing findings geometrically from primitives. Rules: (1) floating pins — a pin is connected iff a wire touches its coordinate (NC-marked excluded), grouped by component as {designator, pins[]} (the exact input schematic.pin.set_no_connect takes); (2) wire-crossing — two wire segments cross in their interiors (a routing tangle; shared endpoints/junctions excluded), reported with the intersection point; (3) wire-over-pin — a pin sits in a wire's interior (EasyEDA trims+connects there → unintended short; enforces the SOP "chain pin→pin, don't run a wire through a pin"). Returns {passed, summary{floatingPins,wireCrossings,wireOverPins,…}, findings[]}. CLI: easyeda sch check (--json, --strict, --all-pages). Verified live via a detect→fix→re-check loop on an ESP32-S3: 2 wire-crossings found and driven to 0.
• schematic.drc.check now returns per-violation detail. Normalizes the SDK result into {passed, fatal, summary, violations[]} — each violation projects {level, rule, message, primitiveIds, designators, x, y} (raw kept) plus a severity summary and a fatal count for the design-flow S5 gate. CLI sch drc prints one line per violation and exits non-zero only when fatal > 0. NOTE: the schematic SDK only provides an aggregate, so detail degrades honestly to "N issue(s) — EDA returned no per-item detail" (use schematic.check for the itemized floating-pin findings).
• schematic.snapshot anti-stale metadata (issue #2). The snapshot result now carries primitiveCount (live components + page primitives on the current page), capturedAt (ISO timestamp), and a stale advisory string. EasyEDA does not auto-redraw after eda.* edits, so getCurrentRenderedAreaImage can return a byte-identical STALE frame; callers compare primitiveCount across two snapshots to detect when the image didn't change but the page did. Judge state by data, use the screenshot for layout only.
• schematic.page.clear — one-shot page reset. Deletes every page-level primitive on the active page (components, net flags/ports/labels, wires, buses, and graphics — arcs/circles/rectangles/polygons/text), not just components. preserveSheet (default true) keeps the sheet/title block; dryRun reports per-type counts without deleting. Returns {deleted:{...}, total, deletedIds}. Fixes the trap where schematic.component.delete left wires/buses behind while components.list reported a clean page, forcing a fall back to raw debug.exec_js.
• schematic.primitives.delete — generalized, any-type delete. Routes each requested id to its owning sch_Primitive* class so wires/buses/graphics/flags can be deleted alongside components; omit primitiveIds to delete the current selection (select-all → delete). Reports notFound ids.

Changed

• Version bump to pair with the daemon/CLI artifact-path change. No connector behavior change vs 0.5.7. The CLI now sends its working directory and the daemon writes artifacts (snapshots, netlist/BOM exports) under <cwd>/.easyeda/artifacts with sortable timestamped names (<YYYYMMDD-HHMMSS>-<kind>-<short>.ext) instead of a flat artifacts/art_<uuid> in the daemon's cwd. Released together to keep CLI and connector on the same version.

Added

• Heartbeat-carried context. The connector now re-reads the active project/document on each heartbeat (~3s) and pushes it to the daemon only when it changed. easyeda daemon health (and project routing) now reflect a UI tab-switch within one interval — previously context refreshed only on connect or as a side effect of running an action, so it lagged the UI until the next command. The initial post-connect push is unconditional; reconnects reset the change-detection signature so they always re-push.

Added

• PCB layout intelligence — pcb.components.arrange (cluster / grid auto-layout seed) and rendered bounding boxes in pcb.components.list.
• PCB layout adjustment — pcb.align, pcb.distribute, pcb.grid_snap, pcb.components.move.
• Board outline (板框) — pcb.outline.set / pcb.outline.get / pcb.outline.clear.
• PCB DRC — pcb.drc.check, normalized to {passed, violations}.